A common technique for detecting errors in digital transmission systems is to use a parity check. Pursuant to this scheme, the data bits at the transmitter are divided into sections or blocks with each block having at least one parity bit. Within each block, the value of the parity bit is selected to make the number of 1's (or 0's) odd or even. The latter is referred to as even parity and the former is referred to as odd parity. Of course, the parities of a series of blocks can be either all odd, all even, or a combination thereof. At the receiver, the parity of each block is calculated and compared with the information carried by each received parity bit to confirm whether or not a bit error has occurred.
The parity calculation for each block is a relatively straightforward matter once the individual data blocks are identified. The identification of data blocks can be a more difficult task, especially in system applications where the data transmission is continuous and error detection circuitry capable of relocating the blocks after a period of garbled transmission is desired. To provide this capability, an easily identifiable pattern of bits in a fixed position relative to the data blocks is added to the bit stream. For example, in systems transmitting a time division multiplexed signal, the data blocks are typically located after first locating the recurring framing bit pattern. While this technique works satisfactorily, identifying the data blocks by first locating the framing bit pattern is inherently a two-step process. However, the cost, required power and physical size of the resulting error detection circuit does not meet the desired objectives of many system applications. This is particularly true where the error detection capability is desired at a digital signal regenerator. Regenerators do not normally require framing recovery circuitry and the available space and power are often limited.
A prior art approach to provide error detection without the need for elaborate data block identification circuitry is to utilize digital signal format having constant accumulated disparity (see, for example, U.S. Pat. No. 4,121,195 to Jessup issued Oct. 17, 1978). The term "constant accumulated disparity" means that over a sufficient period of time the ratio of logical 1's to 0's (or vice versa) is substantially constant. As a result, the presence of bit errors can be monitored by detecting changes in the averaged dc output of a bistable device which toggles on a predetermined bit value. The shortcomings of this method are that either expensive comparators are required to detect subtle dc changes or the size of each data block and, hence, the spacing between parity bits, must be kept small. The former is obviously undesirable from a cost standpoint while the latter decreases the signal transmission efficiency.